-- Copyright James McGill, 2010
-- Author: James McGill (jmcgill@plexer.net)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity mock_ram is
    Port ( address : in  STD_LOGIC_VECTOR (15 downto 0);
           data : out  STD_LOGIC_VECTOR (7 downto 0);
           clock_2mhz : in  STD_LOGIC;
			  clock_8mhz : in STD_LOGIC);
end mock_ram;

-- A mock implementation of a 2^16 byte RAM. Access to the RAM is gated
-- by the 2MHz clock to simulate the BBC Model B's method of sharing
-- RAM between the video card and the CPU. The RAM responds with data that
-- should produce stripes.
architecture Behavioral of mock_ram is
signal ungated_data : std_logic_vector(7 downto 0) := "11111111";
begin
process (clock_8mhz)
begin
  if clock_8mhz'event and clock_8mhz = '0' then
    -- Produce 10 64 pixel stripes.
	 --if address(3) = '1' then
	 --  ungated_data <= x"FF";
	 --else
	 --  ungated_data <= x"00";
	 --end if;
  end if;
end process;

-- TODO(jmcgill): Check polarity here.
--data <= ungated_data when (clock_2mhz = '0') else
--        "00000000";
data <= x"F0"; --ungated_data;

end Behavioral;

